The present invention relates generally to integrated circuit design tools, and, more particularly, to a tool for modifying an initialization (reset) scheme of an integrated circuit.
An integrated circuit design that includes a large number of logic gates and sequential elements such as flip-flops and latches generally has a specific initialization scheme. The initialization scheme places the circuit design into a known state for simulation, since the elements of the circuit design cannot self-initialize. For example, an initialization scheme for a sequential element may involve either setting or resetting the sequential element. The initialization scheme can be applied during power up, at the beginning of simulation, or during operation of the circuit design simulation.
Many design parameters are considered before choosing an appropriate initialization scheme, such as the kind and implementation of the initialization scheme using the available resources, and so on, and then a computer-aided-design (CAD) tool or an electronic-design-automation (EDA) tool is used to implement the chosen initialization scheme.
The initialization scheme can be either synchronous or asynchronous and is implemented using synchronous or asynchronous resettable sequential elements, or combinations thereof. The asynchronous resettable sequential elements are initialized with an external asynchronous initialization signal, whereas, the synchronous resettable sequential elements receive the initialization signal through their data inputs when the clock terminal receives an input clock. The initialization signal may set or reset the sequential elements. The asynchronously resettable sequential elements reset instantaneously independent of the input clock. For proper operation of the integrated circuit design, all of the asynchronous resettable sequential elements must receive the external asynchronous initialization signal within one cycle of the input clock, thus posing a low skew requirement.
However, as integrated circuit designs become more complex, the level of hierarchies and the fan-outs of the sequential elements increases, which make it difficult to meet the skew rate requirements by simply using asynchronously resettable sequential elements. In such cases, reset-buffer trees are implemented to meet the skew rate requirements. The reset buffer trees are pipelined with binary values corresponding to initial states of the asynchronously resettable sequential elements. However, implementation of the reset-buffer trees results in increases in area and power consumption.
Further, the asynchronously resettable sequential elements may be sensitive to glitches and are larger (in size) than synchronously resettable flip-flops. Hence, for a large and complex integrated circuit design, it is preferable to have more synchronously resettable sequential elements. Therefore, it would be advantageous to have a system and method for modifying an integrated circuit design by replacing asynchronously resettable sequential elements with synchronously resettable sequential elements.